1)ADC clockrate,
sample per second(sps)
  ADC clock=
xtal freq.(osc freq.)/division factor
 ADC Prescaler
selection 
| 
 ADPS2 | 
ADPS1  | 
ADPS0  | 
Division Factor  | 
| 
0 | 
0 | 
0 | 
2  | 
| 
0 | 
0 | 
1 | 
2  | 
| 
0 | 
1 | 
0 | 
4  | 
| 
0 | 
1 | 
1 | 
8  | 
| 
1 | 
0 | 
0 | 
16  | 
| 
1 | 
0 | 
1 | 
32  | 
| 
1 | 
1 | 
0 | 
64  | 
| 
1 | 
1 | 
1 | 
128  | 
example:
 XATL =8Mhz,
 division factor=128,    normal conversion = 13 cycles
 ADC clock =
8Mhz /128 = 62500hz = 62.5Khz ==>  T =16us
 sample per
second(sps) = ADC clock/13 = 62500hz/13 = 4807.692hz  ==> T=208us
ADC clock =  200
kHz , SPS=??
 sample per
second(sps) = 200000/13 = 15384.615hz, around 15Khz
example:
ADC clock =  50
kHz , SPS=??
sample per
second(sps) = 50000/13 = 3846.154,  around 3.8Khz
note:
   
 The successive approximation circuitry requires an input clock frequency
between 50kHz and 200 kHz to achieve maximum resolution, 10 bits resolution.
   
 If a resolution of lower than 10 bits is required, the input clock
frequency to the ADC can be higher than 200 kHz to achieve a higher sampling
rate.  At 1MHz it is possible to achieve eight bits of resolution maximum.
example:
XATL =8M hz,  division factor=64(or
128),    normal conversion = 13 cycles
XATL =
    
ADC clock = 8Mhz /64 (or 128) = 125000hz (or 62500hz)
   sample
per second(sps) = 125000hz (or 62500hz) /13 =9615 (or 4807) SPS
example:
System Clock =16M hz, ADC Prescaler = 128, normal conversion
= 13 cycles
System Clock =
    
ADC Clk Freq = 125Khz  ==>T=8uS
   
ADC conversion time = 104us (13 x ADC clk cycles)
   Maximum
sample rate =sample per second(sps)=  1/104us = 9615 samples/second apprx
example:
System Clock =12.8M Hz,  ADC Prescaler = 64,  
normal conversion = 13 cycles
System Clock =
   
ADC Clk Freq = 200Khz,   ==>T=5uS
   ADC
conversion time = 65us (13 x ADC clk cycles)
   Maximum
sample rate = 1/65us = 15385  samples/second apprx
example:
System Clock =8M Hz,  ADC Prescaler = 32,   normal
conversion = 13 cycles
System Clock =
    
ADC Clk Freq = 8MHz/32=250Khz,   ==>T=4uS
   ADC
conversion time = 52us (13 x ADC clk cycles)
   Maximum
sample rate = 1/52us = 19230.77  samples/second apprx
example:
Signal = 4 (or 4Khz or 400Khz or ....)
Sampling rate = 4 (or 4Khz or 400Khz or ....)

example: Signal = 4 (or 4Khz or 400Khz or ....)
Sampling rate = 8 (or 8Khz or 800Khz or ....)
nyquist rule => Sampling rate = 2 X Signal freq.

example: Signal = 4 (or 4Khz or 400Khz or ....)
Sampling rate = 16 (or 16Khz or 1.6Mhz or ....)
nyquist rule => Sampling rate = 4 X Signal freq.

example: Signal = 4 (or 4Khz or 400Khz or ....)
Sampling rate = 3.2 (or 3.2Khz or 320Khz or ....)
under sampling ==> Sampling rate = 4 /5 * Signal freq.

example: Signal = 9 (or 9Khz or 900Khz or ....)
Sampling rate = 4 (or 4Khz or 400Khz or ....)
under sampling ==>Sampling rate = 4 /9 * Signal freq.
example:
Signal = 4 (or 4Khz or 400Khz or ....)
Sampling rate = 4 (or 4Khz or 400Khz or ....)

example: Signal = 4 (or 4Khz or 400Khz or ....)
Sampling rate = 8 (or 8Khz or 800Khz or ....)
nyquist rule => Sampling rate = 2 X Signal freq.
example: Signal = 4 (or 4Khz or 400Khz or ....)
Sampling rate = 16 (or 16Khz or 1.6Mhz or ....)
nyquist rule => Sampling rate = 4 X Signal freq.
example: Signal = 4 (or 4Khz or 400Khz or ....)
Sampling rate = 3.2 (or 3.2Khz or 320Khz or ....)
under sampling ==> Sampling rate = 4 /5 * Signal freq.
example: Signal = 9 (or 9Khz or 900Khz or ....)
Sampling rate = 4 (or 4Khz or 400Khz or ....)
under sampling ==>Sampling rate = 4 /9 * Signal freq.
 
 
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