0.3V 工作 DC/DC 轉換器 (產生5V/2mA , MAX輸出)

0.3V以上工作, DC/DC 轉換器 (產生5V/2mA , MAX輸出)








Versa-Pac transformer



Versa-Pac transformer  VP1-1400-R 機構圖





原文:

http://www.edn.com/design/power-management/4320557/JFET-based-dc-dc-converter-operates-from-300-mV-supply

JFET-based dc/dc converter operates from 300-mV supply

You use a JFET's self-biasing characteristics to build a dc/dc converter that operates from power sources such as solar cells, thermopiles, and single-stage fuel cells, all of which deliver less than 600 mV and sometimes as little as 300 mV. Figure 1 shows the drain-to-source characteristics of an N-channel JFET under zero-bias conditions, which you can produce by connecting its gate and source together. Applying 100 mV causes a current of 10 mA to flow through the device, increasing to 30 mA at 350 mV. Exploiting the JFET's ability to conduct significant current at zero bias makes it possible to design a self-starting, low-input-voltage converter.

The circuit can supply 5V at currents as large as 2 mA—enough to serve many micropowered applications or to provide auxiliary bias for a higher power switched-mode voltage regulator. At 300-mV input, the circuit starts up at load currents of 300 µA. A load current of 2 mA requires an input of 475 mV.

In Figure 2, Q₁, a parallel-connected pair of Philips Semiconductor's (www.semiconductors.philips.com) BF862 JFETs, and Coiltronics' (www.coiltronics.com) Versa-Pac transformer(http://datasheet.octopart.com/VP1-1400-R-Coiltronics-datasheet-11474.pdf), T(VP1-1400-R₎, form an oscillator in which T₁'s secondary winding provides feedback to Q₁'s gate. When you first apply power, Q₁'s gate rests at 0V, and drain current flows through T₁'s primary winding. T₁'s phase-inverted secondary winding responds by delivering a negative voltage to Q₁'s gate, which turns off Q₁ and interrupts current flow through T₁'s primary winding. In turn, T₁'s secondary voltage collapses, and sustained oscillations begin. Although the BF862's published specifications do not cover the device's internal geometry, the device has a low on-resistance and maintains a low gate-turn-on threshold voltage. Using a pair of parallel-connected JFETs for Q₁ ensures the low saturation voltage for operation at low power-supply voltages.

Rectifying and filtering the positive-going flyback-voltage impulses on Q₁'s drain produce a dc voltage across capacitor C₁. To assist the circuit's start-up, a P-channel MOSFET, Q₂, which requires a gate-to-source voltage of approximately 2V for conduction, initially isolates the output load from the rectifier. When Q₂ conducts, the output voltage increases toward 5V. Comparator IC₁, a Linear Technology (www.linear.com) LTC-1440, draws power from Q₂'s source and imposes output-voltage regulation by comparing its internal voltage reference with a sample of the output voltage. The output from IC₁ varies Q₁'s on-time through Q₃ to close the control loop and maintain output-voltage regulation. Figure 3 shows the ripple voltage present at the power supply's output. When the output voltage decays, comparator IC₁ switches (Trace B, middle) and allows Q₁ to oscillate. The resulting flyback events at Q₁'s drain (Trace C, bottom) restore the output voltage.

Using Q₃ as a simple but effective shunt control for Q₁'s gate voltage results in a 25-mA quiescent-current drain from the power source. A modification reduces the quiescent drain to 1 mA (Figure 4). Inserting switch Q₄ in series with T₁'s secondary winding more efficiently controls Q₁'s gate. Bootstrapping the voltage across T₁'s secondary winding produces negative-turn-off-bias voltage for Q₄. Figure 5 illustrates how to connect T₁'s windings. When Q₄ switches off, it interrupts the current flowing in T₁'s secondary winding and drives T₁'s Pin 5 positive. Without diodes D₄ and D₅, the peak voltage would approach 15V and reverse-bias Q₄, an undesirable condition. Under normal operating conditions, excursions of approximately 0.8V appear at Pin 5, necessitating the use of two series-connected diodes to clamp the voltage at a safe level. Zener diode D₃ holds off bias-supply loading to aid start-up during initial power application.

datasheet download:
TP0610L : P-Channel 60V 0.18A 0.8W  (D-S) MOSFET
http://www.vishay.com/docs/70209/70209.pdf

2N7002K (取代 VN2222LL) : N-Channel 60-V (D-S) MOSFETs with Zener Gate

http://www.vishay.com/docs/70212/70212.pdf

http://www.vishay.com/docs/71333/2n7002k.pdf

LTC-1440 : Ultralow Power Single/Dual Comparator with Reference

http://cds.linear.com/docs/Datasheet/144012fd.pdf

BAT54-V(取代 BAT85S) : Small Signal Schottky Diode

http://www.vishay.com/docs/85513/bat85s.pdf

http://www.vishay.com/docs/85508/bat54v.pdf

note:

補充1: BF862 spice model

*   BF862 SPICE MODEL MARCH 2007 NXP SEMICONDUCTORS
*   ENVELOPE    SOT23
*   JBF862: 1, Drain,  2,Gate,  3,Source

  Ld  1 4  L= 1.1nH
  Ls  3 6  L= 1.25nH
  Lg  2 5  L= 0.78nH
  Rg  5 7  R= 0.535 Ohm
  Cds  1 3  C= 0.0001pF
  Cgs  2 3  C= 1.05pF
  Cgd  1 2  C= 0.201pF
  Co  4 6  C= 0.35092pF

JBF862  model parameters:

.model JBF862 NJF(Beta=47.800E-3 Betatce=-.5 Rd=.8 Rs=7.5000 Lambda=37.300E-3 Vto=-.57093
+ Vtotc=-2.0000E-3 Is=424.60E-12 Isr=2.995p N=1 Nr=2 Xti=3 Alpha=-1.0000E-3
+ Vk=59.97 Cgd=7.4002E-12 M=.6015 Pb=.5 Fc=.5 Cgs=8.2890E-12 Kf=87.5E-18
+ Af=1)

補充2: BF862 LTspice model

.model BF862 NJF(Beta=47.800E-3 Betatce=-.5 Rd=.8 Rs=7.5000 Lambda=37.300E-3 Vto=-.57093
+ Vtotc=-2.0000E-3 Is=424.60E-12 Isr=2.995p N=1 Nr=2 Xti=3 Alpha=-1.0000E-3
+ Vk=59.97 Cgd=7.4002E-12 M=.6015 Pb=.5 Fc=.5 Cgs=8.2890E-12 Kf=87.5E-18
+ Af=1 mfg=nxp)

補充3: 

1)TP0610L 第三方model (LTspice 採用 “.MODEL” 及“.SUBCKT” 語法)

http://www.vishay.com/docs/78526/tp0610k_.lib (這是“.SUBCKT” 語法) 

勿忘於LTspice 電路中使用SPICE Directive 功能鍵加入 ".inc TP0610K.lib" 語法.

2) BAT54-V 之 LTspice model

 .model BAT54 D(Is=.1u Rs=2.2 N=1 Cjo=12p M=.3 Eg=.69 Xti=2 Iave=300m Vpk=30 mfg=Vishay type=Schottky)

3) 2N7002K 之 第三方model 

http://www.vishay.com/docs/78742/2n7002k_.lib (這是“.SUBCKT” 語法) 

勿忘於LTspice 電路中使用SPICE Directive 功能鍵加入 ".inc 2n7002k.lib" 語法.

補充4:

在 LTspice IV 中使用變壓器器

在許多需要採用反激式、正激式和 SEPIC 轉換器的開關穩壓器設計中，變壓器及耦合電感器是重要的組件。它們在提供隔離勢壘、實現高降壓或升壓比、以及提供多輸出或負輸出方面起到了至關緊要的作用。

雖然可以針對某個特定的變壓器製作專用的子電路，但 LTspice 優選的方法則是為每個變壓器繞組指定一 個單獨的電感器，然後通過單個互感 (K) 運算式將它們磁耦合在一起。

本視頻將概述怎樣定義一個採用電感器的變壓器及通過一個 K 運算式來規定互感，最後說明如何給仿真 增設多個繞組。 http://video.linear.com.cn/93

補充5:
给 LTspice IV 添加第三方模型

LTspice IV 可提供众多的器件模型，包括诸如晶体管和 MOSFET 等分立器件的模型。不过，它还拥

有许多由其他制造商提供的第三方模型，您可以把它们添加至自己的 LTspice IV 电路仿真中。此类

第三方 SPICE 模型采用 “.MODEL” 和 “.SUBCKT” 语句来表述。被赋予 “.MODEL” 语句的模型

用于固有 SPICE 器件 (例如二极管和晶体管)。而被赋予 “.SUBCKT” 语句的模型则利用固有 SPICE 

器件的电路结集来定义组件。 

本视频概要说明了怎样为 LTspice IV 增添一个用于固有 SPICE 器件的第三方“.MODEL” 语句、以

及如何添加和创建一个用于第三方 “.SUBCKT” 语句的符号。 
http://video.linear.com.cn/97 

補充6:

变压器在LTspice四

http://cn.edaboard.com/topic-2175600.0.html