Time-to-Digital Converters and Timing Circuits

http://www.infotech.oulu.fi/Annual/2009/cas.html

Circuits and Systems (CAS-Oulu)Professor Juha Kostamovaara and Professor Timo Rahkonen,
Electronics Laboratory, Department of Electrical and Information Engineering, University of Oulu

juha.kostamovaara(at)ee.oulu.fi, timo.rahkonen(at)ee.oulu.fi
http://www.infotech.oulu.fi/cas

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Background and MissionThe Circuits and Systems group consists of about 30 researchers working at the Electronics Laboratory of the Department of Electrical and Information Engineering at the University of Oulu. Its main activity is in the field of electronic and optoelectronic circuit and system design. The primary implementations are based on various ASIC technologies. The main interest of the group is devoted to certain novel circuit topologies and functional units, although the group is also interested in applications, especially in the field of telecommunications and electronic/optoelectronic measurements.
The main research fields are:

• time-to-digital converters and timing circuits
• generation and detection of powerful and high-speed electrical and optical pulses/transients, breakdown phenomena in semiconductors in general
• development of pulsed time-of-flight laser range finding technologies especially for industrial applications
• radio telecommunications including linearization of power amplifiers, AD/DA conversion and baseband blocks, frequency synthesis

The group has created a well-functioning partnership with some international research units working in the same or in a complementary field. The group is mainly funded by the Academy of Finland, Tekes and industry.

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Scientific Progress
In the following, some details and results of the work of the group are given in chosen important research fields.

Time-to-Digital Converters and Timing Circuits
6-Channel Time-to-Digital Converter CMOS Chip Based on Multi-Phase Delay Line Interpolation
A 6-channel time-to-digital converter (TDC) circuit is under development and targeted especially to pulsed time-of-flight laser range-finding studies. Time-to-digital conversion is based in this circuit on a counter and stabilized delay line interpolation, which combined provide for a ms-level linear dynamic range, stable ps-level LSB resolution and good temperature stability. The TDC has autocalibration, i.e. the resolution of the TDC is locked to the cycle time of the external reference oscillator. No additional calibration cycles are thus needed during the measurement.
In its main operation mode, the TDC digitizes the arrival time of the rising edge of the start pulse, and the rising and falling edges of a maximum of three stop pulses in one stop channel, as shown below. The measurement results are referenced to the arrival time of the start signal. By measuring the arrival time of both edges of the stop pulses, the pulse positions (T_SP1-T_SP3) and widths (T_w1-T_w3), which may be proportional to the widths of the detected analog receiver signals; for example, they can be determined for three separate stop signals. In pulsed time-of-flight laser ranging, these separate stops might represent the echoes from the case window, the effect of rain at the distance where the optics is most sensitive and from the wanted object, for example. Pulse width measurement enables one to compensate the timing walk error induced by varying echo amplitudes.

Timing diagram of the 6 channel CMOS TDC.

The 6-channel TDC is based on a TDC core that is shown in detail in the next figure (only one interpolator shown).

Time-to-digital converter architecture.

The first coarse interpolation level creates many small, even length time samples inside each reference clock cycle. The interpolator recycles the reference clock rising edge in a short (a small number of cascaded delay element) delay line many times during each reference clock period. After N recycling rounds a new, jitter-free reference edge is transmitted to the delay line and the recycling begins again. The recycling is realized by connecting the end of the delay line to the first element with a multiplexer, as shown in the first figure. This multiplexer is controlled with a counter, which counts the recycling rounds. A small number of delay elements improves the integral nonlinearity of the delay line. The reference clock frequency can be decreased simultaneously by increasing the number of recycling rounds N. The cascaded delay elements produce time samples with an even time margin (τ₁), when the recycling signal propagates in the delay line. The incoming timing signals (start and stop) record the states of the delay line, and control (enable and disable) the counter, which counts the rounds of the recycling delay line between the timing signals. This interpolation structure with a counter makes long range time interval measurement possible with the resolution of delay element delay τ₁.
Time interval measurement resolution of one delay element unit delay (τ₁ ≈ 350 ps @ 0.35 µm CMOS) can be achieved with the interpolation structure mentioned above. In order to achieve higher resolution, sub-gate-delay interpolation structures have to be used. The second interpolation level (fine interpolator) interpolates the location of the timing signal within the result of the first interpolation level. The region of the result of the first level (τ₁) is interpolated with ~10 ps resolution by utilizing a parallel load capacitor-scaled delay line structure. The synchronized result from the coarse interpolator (sync-signal) creates 8 parallel time samples with τ₂ ≈ 10 ps resolution. Simultaneously the delayed, asynchronous timing signal (start or stop) creates 8 time samples with 6τ₂ ≈ 60 ps time difference. The coincidence of these time samples is registered and defines the second interpolation level result.
The measured performance of the developed TDC core is presented in the table below.



Time-to-Digital Converter CMOS Chip Based on Time Domain Successive Approximation Interpolation
A time-to-digital converter (TDC) with ~1.2 ps resolution and ~327 µs dynamic range was also developed. The resolution of ~1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method utilizing a pair of digital-to-time converters (DTC), the propagation delay difference between which is implemented by digitally controlling the unit load capacitors of their delay cells. The rms single-shot precision, i.e. standard deviation σ-value of the TDC is 3.2 ps, which is achieved by minimizing the measurement errors caused by the integral nonlinearity (INL) of the interpolators with a correction look-up table (INL-LUT) containing the measured INLs of the interpolators. The power consumption is 33 mW at 100 MHz with a 3.3 V operating voltage. The prototypes were fabricated in a 0.35 µm CMOS process.
The next figure shows schematically the operation principle of the time domain successive approximation algorithm for 4 bits, and the second figure the corresponding electrical realization for 8 bit interpolator.

Operating principle of a 4-bit CTDSA method as a timing diagram.

Realization of an 8-bit CTDSA interpolator.

Time-to-Digital Converter Board Achieving 1 ps Measurement Precision
A time-to-digital converter based on time-to-amplitude interpolation was designed and tested. The converter was implemented with discrete components. The measurement range is about 0-328 µs with a state-of-the-art single shot precision of 1.5 ps. The time interval is measured by counting full clock cycles with a counter implemented in an FPGA circuit and the fractional time residue is then measured with time-to-amplitude converters that provide the picosecond level precision. The block diagram of the TDC is presented in the next figure and the actual realization below it.

Simplified block diagram of the TDC based on time-to-amplitude interpolation.

The TDC board (10 cm * 10 cm).

The interpolators consist of a constant current source, a fast switch, a Miller integrator and offset compensation circuitry. The interpolator charges a capacitor with a constant current during the fractional time residue. The output voltage of the interpolator is then AD converted and combined with the result of the full cycle counter. With a reference clock of 200 MHz the measurement range of a single time-to-amplitude interpolator is 5 ns. All the bias voltages are produced by DA-converters that can be controlled via software.
The nonlinearities of the interpolators reduce the single-shot precision to about 1.5 picoseconds. The integral nonlinearities of the TACs are shown in the next figure. When this systematic error is compensated, single-shot precision can be improved to ~1 ps.

INL of the time-to-amplitude converter.

The next figure shows the distribution of measurement results when a constant delay of 15 ns was measured. The standard deviation of the results corresponds to a single-shot precision of 1.3 ps. No INL correction was done to the results. This result is believed to represent the state-of-the-art among published time-to-digital converters.

Distribution of the time interval measurement results with constant input time interval.

A receiver channel topology for a pulsed time-of-flight laser range finder has been developed, fabricated and measured and is now under system tests. The timing detection is based on the leading edge detection in the receiver channel, which makes possible a very wide dynamic range for the input pulse current signal. The receiver channel has been realized in a 0.35 µm SiGe BiCMOS process.
The compensation principle utilizes the time-to-digital converter (TDC) to perform the compensation of the walk error. The walk compensation principle is based on the measurement of the pulse length of the received optical pulse. The simplified block diagram of the receiver channel is shown next.

Block diagram of the integrated laser radar receiver channel.

Based on the measurements, the bandwidth and the transimpedance of the receiver channel are 230 MHz and 11 kΩ, respectively. The input referred rms noise current was < 100 nA, thus the minimum signal of ~1 µA is required for the SNR of 10. The maximum measured input current was about 100 mA. Thus the input current varies at the range of 1 : 100 000. In this dynamic range, the uncompensated walk error was about 1.8 ns, while the use of compensation the error was reduced to be less than ±20 ps.
Integrated Laser Radar Chip
A CMOS laser radar chip including an optical receiver channel and a time to digital converter (TDC) integrated onto the same die and realized using a 0.13 µm CMOS technology has been fabricated and tested, and is also under system tests now. A block diagram of the receiver chip for a pulsed TOF laser rangefinder with I/O pads is shown below. The optical pulse is first converted to a current pulse in an external photodetector, and then amplified in a transimpedance preamplifier (Z) and further amplified in a voltage-type postamplifier (A). Two timing comparators with different thresholds, V_th1 and C*V_th1 (generated by DAC1 and DAC2), are used to generate the logic-level timing marks STOP and STOPtr. The TDC has separate channels to measure the START-STOP time interval used to calculate the distance to the target and the STOP-STOPtr time interval (proportional to the slew rate) used to correct the timing walk error caused by the varying amplitude of the received pulse. This, of course, necessitates the use of a look-up table or a fitting calibration curve, which contains time walk information collected during calibration of the receiver.

Block diagram of the CMOS laser radar chip.

A photograph of the receiver is shown next. The size of the layout of the receiver is 1300 µm x 1300 µm. The operation frequency of the ring oscillator was 1.1 GHz, giving a resolution (LSB) of 14 ps for the TDC corresponding 2 mm in distance, with the total power consumption of 45 mW.

A photograph of the CMOS laser radar chip.

The bandwidth and the transimpedance of the channel were 300 MHz and 23 kW, respectively. The input referred rms noise current was < 100 nA_rms (C_d = 1.5 pF). The uncompensated walk error was about 2.2 ns in the input current range of 2 µA to 20 mA while the use of the compensation reduced it to less than ±30 ps. The total accuracy of the receiver is better than ±5.5 mm in the distance range of 0.75 m - 15 m including both the nonlinearity of the TDC and the walk error of the receiver channel.

Generation of Electrical/Optical Transients

High Pulse Power CMOS Laser Diode Driver
Discrete power MOSFETs can be used to generate ampere-scale current pulses with a short rise time (~ 2-3 ns). However, charging and discharging the large gate capacitance can be a problem when using a power MOSFET as a nanosecond switch, necessitating at least the use of high current drivers to load the gate capacitance fast enough. This can be a crucial disadvantage in applications which require small size. In addition, power MOSFET switches need a relatively high gate voltage to switch the device on. Also avalanche transistors and step recovery diodes can be used to generate fast pulses but unfortunately require even higher bias voltages.
An integrated CMOS current pulse generator was designed, achieving an ampere-scale peak current pulse with a rise time and pulse width of less than 1 ns and 2.5 ns (PWHM) with only 5 V power supply. The generator is implemented in a 0.35 µm CMOS process and consists of four parallel NMOS transistors driven by a scaled buffer chain to achieve fast switching. The schematic of the pulser is shown in the next figure. Optical pulse power of approximately 450 mW is achieved by using a CW semiconductor laser diode (Thorlabs L904P030) as is shown in the second figure.

Schematic of the CMOS laser diode pulser.

Optical pulse response of CW laser diode.

High Power Picosecond Laser Pulse Generation with an Asymmetric Waveguide Laser Diode 
A semiconductor laser with a strongly asymmetric waveguide structure and a relatively thick (~ 0.1 micrometers) active layer was designed, fabricated and tested for the purpose of achieving short (~100 ps) and high-energy (> 1 nJ) optical pulses by gain switching. The laser diode structure was tailored to use an easily realizable, inexpensive current pulsing circuit. The active layer was positioned asymmetrically to provide a very small optical confinement factor Γ_a (the next figure). The combination of a relatively large active layer thickness d and a small Γ_a ensured a very large equivalent spot size d/Γ_a leading to large optical pulse generation with a ~2 ns FWHM, ~10 A injection current pulse.

The waveguide structure of the proposed laser and the corresponding modal intensity distribution.

The next figure shows the measured laser pulse intensity and wavelength as a function of time with three input current pulse amplitudes. As predicted by the theoretical studies, a high power single pulse of a length of about 100 ps can be achieved. The position of the laser pulse in relation to the current pulse can be seen in the PIN-diode measurement result of the second figure.

Streak camera measurement results with three current pulse amplitudes (LD stripe imaged completely on streak camera cathode).

15 GHz PIN-diode measurement result with four current pulse amplitudes.

Picosecond Laser Transients in SH Laser Diodes
A very high power density in the picosecond lasing mode was obtained from a specially designed and fabricated laser diode structure based on heavily doped layers of GaAs /AlGaAs system.

A 50 W / 30 ps optical pulse generated near the trailing edge of the pumping current pulse at room temperature. The area of the laser diode chip is 400 µm × 20 µm (length × width).

This laser diode can be pumped with a commercial Si avalanche transistor (ABJT), which makes this result very interesting for applications. Even though Si avalanche transistors have commercially been utilized for many years, we have lately shown that there are 3-D phenomena, which affect drastically transistor operation in short-pulsing mode; this was not previously known. Particularly important is the finding that the length of the emitter-base interface participating in the switching is controlled by the value of the capacitor to be discharged across the switch. This phenomenon determines many peculiar features of ABJT in different circuits, and should be taken into account in both circuit and transistor chip designs.
Important for picosecond laser design is the correlation, which we recently found, between the breakdown voltages of the p-n junction of SH laser diode and its addiction to high-power picosecond pulse generation. Namely, a gradual p-n junction comprised in a SH structure causes picosecond lasing, while SH structure with an abrupt p-n junction provides quasi-steady-state lasing. Careful verification and practical utilization of this completely unexpected behavior is currently a subject of further study.
Superfast High-Voltage Switch Based on a GaAs BJT Structure
Interesting new results have been achieved in the course of experimental and theoretical investigation of the switching transient in specially designed and fabricated GaAs avalanche transistors. A superfast (~200 ps) switching transient was observed and an original physical interpretation of the phenomenon was suggested. The superfast switching originates from the switching channel of a comb of moving and avalanching field domains of ultra-high amplitude (the next figure). These domains cause fairly homogeneous and extremely powerful carrier generation along the whole length of the switching channel. Increase in the carrier density causes drastic reduction ("collapsing") in the domain width, thus reducing the voltage across the device, while the domain amplitude remains extremely high (by a factor of 2 to 3 higher than the ionization threshold) thus supporting a powerful ionization rate even at a reduced voltage across the transistor.

(a) – measured and simulated voltage and current across a GaAs avalanche transistor, (b) - simulated electric field profiles at various instants across the structure (along the switching channels in the direction of the current flux); the instants shown in (b) correspond to the time scale in (a).

This train of the collapsing domains appears provided that two non-trivial conditions are satisfied: (i) an active semiconductor layer is biased with an electric field comparable with the ionization threshold (E_i ≈ 2×10⁵ V/cm), and not only at the threshold of the Gunn effect (E_t ≈ 4×10³ V/cm); (ii) negative differential mobility (NDM) takes place not only near the threshold of the Gunn effect, but lasts well beyond the ionization threshold. The electron transport in GaAs beyond the ionization threshold is an open question, and existing theoretical data are contradictory. We have performed Monte Carlo simulations of the electron transport in an extreme field and its experimental verification in a GaAs BJT operating in avalanche mode. Application of data obtained from different Monte Carlo simulations to the modelling of the transient in a GaAs avalanche BJT has allowed a conclusion to be made that NDM in GaAs takes place at least up to an electric field of 600 kV/cm, while earlier it was believed that the differential mobility changes its sign from negative to a positive one already at 350 kV/cm. This result related to the fundamental properties of GaAs is of major importance for various processes in ultra-high electric fields.
Furthermore, we have also shown very recently that the switching efficiency, stability and reliability can be controlled by a simple increase in the emitter area of the transistor chip, and we performed a detailed comparison of the experimental and simulated results. This result together with significant practical soundness is very interesting. The point is that an elevated area of the emitter, which is not participating in the switching itself, still supplies circuital currents inside the switching channels, thus increasing the ionization rate and switching efficiency, and providing perfect switching synchronization of multiple channels. An advanced model has also allowed the solving of the spatial/transient thermal task for a GaAs superfast switch for the first time. The results show that increasing in the transistor area allows the temperature in the hottest points of the switching channels to be reduced practically twice, thus improving the device reliability.
THz Emission from a GaAs BJT Structure During Its Avalanche Switching
Another very promising application for the avalanche switching mode in GaAs BJT is the generation of pulsed broad-band terahertz emission. Periodical nucleation and annihilation of ultra-narrow, ionizing domains is believed to cause the THz emission observed in our experiment. The measured emission power observed in the BJT operating in pulsed (~2 ns) mode was rather high (in the sub-milliwatt range), while even much higher power was predicted in the simulations, see details in the next figure.

An example of the bolometer response to a switching of a GaAs avalanche transistor chip situated at a distance of 90 mm from the bolometer input without any collimating optics. A gray curve presents the current pulse across a GaAs ABJT, the black curve shows the NbN bolometer response, and colored curves show how the bolometer response is modified by passing of a sub-THz signal through rectangular metal meshes of different shell size and at different rotation angles.

Circuit Analysis Techniques and Results

Volterra-on-Harmonic Balance Analysis
The development of a Volterra-on-Harmonic Balance (VoHB) simulation algorithm continued in the EU project Icestars. Previously, the algorithm has been implemented using the I command language of an Aplac circuit simulator, but now AWR-Aplac has presented a function interface AIF that allows C-language access to many internal functions and data structures of Aplac, including the complete circuit matrix, and input and output signals of the VCCS sources that constitute all device models in Aplac. Hence, for the first time, a truly generic multi-device VoHB algorithm was coded and has been tested for circuits larger than plain single-transistor PA's. For example, the next figure shows the distortion contributions of a 2-transistor LNA, where Q2 clearly dominates the distortion (contributions from Q1 are very small). Thanks to the operation at the VCCS level (i.e., below the device model level) the analysis is now independent of the device simulation model used, and there is no need to modify the models to make the VoHB analysis possible.

IM3 distortion contributions of a 2-transistor LNA, showing the responses of transistors Q1 and Q2, simulated using C implementation of the VoHB algorithm.

One application example of the VoHB was also in included in the Microwave Theory and Techniques article "A Comprehensive Analysis of AM-AM and AM-PM Conversion in an LDMOS RF Power Amplifier". In addition, the Volterra-assisted harmonic load pull technique developed during 2008 was reported in the European Microwave Conference.

Telecommunication Electronics

Supply Modulated RF Transmitters
The research on supply modulated RF transmitters proceeded in several ways. A journal paper on different supply drive strategies was published in Wiley International Journal of Circuit Theory and Applications, and a new, more detailed study on the effect of timing mismatch between RF and supply signals was published in the European Microwave Conference. Finally, a new supply modulator was developed, this time using an ADSL driver opamp as the linear stage. At the end of the year T. Rautio MSc started writing his Lic. Tech thesis on the signal processing needed for supply modulated transmitters.
The next figure shows the measured upper and lower ACP level in an envelope tracking transmitter, where the delay between RF and supply signal has been varied. A QAM test signal with varying bandwidth was used in the tests. Different minima of the lower and upper ACPR curves are caused by severe AM-PM distortion in the LDMOS amplifier used. When it is corrected by predistortion, the curves align.

ACPR of an envelope tracking transmitter as a function of delay between RF and supply signals.

Switching RF Power Amplifiers 
The previously developed 1.6 GHz RF amplifier IC was tested further with a load pull setup, when S. Hietakangas MSc spent two months in Technical University of Trondheim, Norway. Both the load and source impedances were swept to optimize the design, and the effects of harmonic matching were studied. The implemented amplifier needed quite heavy damping at the input side to guarantee stability, and to verify the need for the stabilization, one chip was tested without the stabilization network. The next figure shows that the circuitry was indeed needed: almost with any inductive output load the amplifier developed serious modulation sidebands or full-scale oscillation. Typical of switching amplifiers, the sensitivity to oscillation increases with reduced input drive, and this will be studied in more detail during 2010.
One of the results of the study was that the lumped presentations of switching amplifiers do not match well with reality, as physical distance and the type and Q-value of the impedance matching network greatly affect the pulse shaping. This has been studied by normalized sweeps of the load impedance.

Output loads resulting in spurious sidebands or oscillation, when the input damping network of the RFIC PA is disconnected.

Digital Error Correction of AD Converters 
Multi-bit sigma-delta AD and DA converters employ various mismatch noise shaping algorithms to randomize the INL o, but the comparison of these is difficult due to the random nature of mismatch errors: the mismatch randomizer may work fine with some type of linearity error and worse with others. To make the development of the techniques repeatable, a systematic approach based on a limited set of polynomially shaped DNL errors was developed for testing and comparing DAC mismatch shaping methods, and published in the ECCTD conference. Moreover, a simple and generic Simulink simulation model for a generalized low-pass and bandpass data weighted averaging was developed, and it was accepted for publication in IEEE Trans on Circuits and Systems.
On-Chip Testing of DAC and ADC Static Linearity
Static linearity (INL and DNL) of ADCs and DACs are important parameters in various applications, but testing of these parameters is a time consuming task. Traditionally the testing of high resolution converters requires expensive external test equipment, and a long test time with expensive equipment is an unwanted combination. Cost-effective built-in testing without external equipment is one solution for the problem but new test techniques are required for this purpose.
In this work, a new calculation algorithm is developed which can be used to find the INL and DNL of an ADC without accurate test stimulus. The algorithm is much simpler than previous proposals, but it also enables all digital INL testing of both, D/A and A/D, converters in a loopback configuration shown in the next figure.

An all-digital loopback test setup.

The offset generator between the converters is an essential part of this test technique and its accuracy defines the maximum accuracy of INL measurement. It is shown, in this work, that the offset generator can be a very simple resistive adder with very small area overhead. Using high-ohmic poly resistors of a 130 nm HCMOS process by ST-Ericsson, the area overhead of the generator is just 0.0035 mm² and it can be used to test the INL of 12-b converters as the measurement results show below.

Actual and measured INL.

Frequency Synthesis Using DS Phase-to-Digital Converter 
A concept of a multi-bit ΔΣ phase-to-digital converter (PDC) is proposed to digitize the phase-locked loop, see below. The PDC is a 2-stage ΔΣ modulator in the phase domain. The first stage is mainly a modulus counter as a coarse phase quantizer, whose phase quantization step is 2π. The second stage is an analogue of the multi-bit 1st-order ΔΣ analog-to-digital converter in the phase domain. Its quantization step is defined by the ratio of time resolution of the digital-to-time converter to the VCO period time. Compared with a conventional ΔΣ fractional-N frequency synthesizer, a DPLL using this PDC has greatly reduced quantization phase noise both at close-in band and out-of-band.
The proposed architecture is verified with a MATLAB SIMULINK model. An event-driven model using pure VHDL language is developed for fast behavior simulation. This VHDL model is further expanded using VHDL-AMS to count in various analog effects.

ΔΣ phase difference quantizer.

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Personnel

professors & doctors	7
graduate students	15
others	8
total	30
person years	22

External Funding

Source	EUR
Academy of Finland	487 000
Ministry of Education	83 000
Tekes	153 000
domestic private	103 000
international	149 000
total	975 000

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Selected Publications
Nissinen I & Kostamovaara J (2009) On-chip voltage reference-based time-to-digital converter for pulsed time-of-flight laser radar measurements. IEEE Transactions on Instrumentation and Measurement 58(6): 1938-1948.
Nissinen J, Nissinen I & Kostamovaara J (2009) Integrated receiver including both receiver channel and TDC for a pulsed time-of-flight laser rangefinder with cm-level accuracy. IEEE Journal of Solid-State Circuits 44(5): 1486-1497.
Kurtti S & Kostamovaara J (2009) Laser radar receiver channel with timing detector based on front end unipolar-to-bipolar pulse shaping. IEEE Journal of Solid-State Circuits 44(3): 835-847.
Jansson J, Mäntyniemi A & Kostamovaara J (2009) Synchronization in a multi-level CMOS time-to-digital converter. IEEE Transactions on Circuits and Systems - I: Fundamental Theory and Applications 56(8): 1622-1634.
Ryvkin B, Avrutin E & Kostamovaara J (2009) Asymmetric-waveguide laser diode for high-power optical pulse generation by gain switching. IEEE/OSA Journal of Lightwave Technology 27(12): 2125-2131.
Mäntyniemi A, Rahkonen T & Kostamovaara J (2009) A CMOS time-to-digital converter (TDC) based on a cyclic time domain successive approximation interpolation method. IEEE Journal of Solid-State Circuits 44(11): 3067-3078.
Nissinen J & Kostamovaara J (2009) A 1 A laser driver in 0.35 µm complementary metal oxide semiconductor technology for a pulsed time-of-flight laser rangefinder. Review of Scientific Instruments 80(10): 104703-104703-4
Kozmin K, Johansson J & Kostamovaara J (2010) A low propagation delay dispersion comparator for a level-crossing AD converter. Analog Integrated Circuits and Signal Processing 62(1): 51-61.
Korhonen E, Carsten W & Kostamovaara J (2010) Combining the standard histogram method and a stimulus identification algorithm for A/D converter INL testing with a low-quality sine wave stimulus. Accepted to be published in IEEE Transactions on Circuits and Systems I.
Vainshtein S, Yuferev V, Kostamovaara J, Kulagina M & Moilanen H (2010) Significant effect of emitter area on the efficiency, stability and reliability of picosecond switching in a GaAs bipolar transistor structure. IEEE Transactions on Electron Devices 57(4): 733-741.
Hallman LW, Ryvkin B, Haring K, Ranta S, Leinonen T & Kostamovaara J (2010) Asymmetric waveguide laser diode operated in gain switching mode demonstrates high power optical pulse generation. Accepted to be published in Electronics Letters.
Aikio J & Rahkonen T (2009) A comprehensive analysis of AM-AM and AM-PM conversion in an LDMOS RF power amplifier. IEEE Trans. on Microwave Theory and Techniques 57(2): 262-270.
Rautio T, Harju H, Hietakangas S & Rahkonen T (2009) Envelope tracking power amplifier with static predistortion linearization. Wiley International Journal of Circuit Theory and Applications 37(2): 365-375.
Kursu O, Kruusing A, Pudas M & Rahkonen T (2009) Piezoelectric bimorph charge mode force sensor. Elsevier's Sensors and Actuators A: Physical 153(1): 42-49.
Neitola M & Rahkonen T (2010) A generalized data weighted averaging algorithm. Accepted to IEEE TCAS-II.
Hietakangas S, Typpö J & Rahkonen T (2010) Design of integrated 1.6 GHz, 2W tuned RF power amplifier. Accepted to Springer Journal of Analog Integrated Circuits and Signal Processing.