Switch-Mode Power Supplies---SPICE Simulations and Practical Designs
Christophe P. Basso5/10/2008 1:45 PM EDT
The following text, which focuses on feedback and control loops, is excerpted from Chapter 3 of the book Switch-Mode Power Supplies—SPICE Simulations and Practical Designs, by Christophe P. Basso. Reprinted with permission from McGraw-Hill, copyright 2008. McGraw-Hill offers our readers a 20 percent discount on this book. Click here for more information.—VJB
For nearly 100 percent of the applications, a switch-mode converter delivers a parameter—a voltage or a current—whose value must remain constant, independent of various operating conditions, such as the input voltage, the output loading, the ambient temperature. To perform such a task, a portion of the circuit must be insensitive to any of the above variations. This portion is called the reference, usually a voltage source, Vref, which is precise and well stable over temperature. A fraction (α) of the converter output variable (for instance, the output voltage Vout) is permanently compared to this reference. Thanks to a loop that feeds the information back to it, hence the term feedback loop, the controller strives to maintain the theoretical equality between these two levels (Eq. 3-1):
If you go through some power electronics books, you often see the converter modeled using the classical feedback representation. This approach can sometimes confuse the reader as the network divider featuring the α ratio appears in the chain. Unfortunately, if the ratio surely plays a role in setting the dc output, because of the op amp and its virtual ground, its action disappears in the ac analysis. This is discussed in greater detail in App. 3D.
Figure 3-1a portrays the simplified switch-mode converter as it appears on your bench. As we said, thanks to the error amplifier, the whole loop strives to satisfy Eq. (3-1).
Based on Fig. 3-1a, we can draw Fig. 3-1b as a simplified static representation where we purposely reduce the whole chain in a unity-return configuration. From this new drawing, we can write a few equations (Eqs. 3-2):
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Figure 3-1a: A simplified schematic of the switch-mode power converter operating in closed-loop mode.
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Figure 3-1b: A simplified static representation of the switch-mode converter.
Here T(0)
represents the static loop gain linking Vout and Vref. The term T(0)/(1 + T(0)) illustrates the static error between the theoretical output value you want and the final measurement you read with a voltmeter once the loop is closed. This is something already seen in Chap. 1. Thus, using a large open-loop gain op amp is key to reducing the static error, but it also helps to provide enough low-frequency gain to fight the rectification ripple in off-line supplies.
Figure 3-2 illustrates the small-signal representation of the power supply. As we explained, the op amp keeps its noninverting pin to zero in small-signal conditions. Therefore, Rlower naturally fades away, and the loop gain is solely fixed by Rupper and Zf. Changing the divider network ratio (α) has no effect on the loop gain, as demonstrated in App. 3D. This is what Fig. 3-2 suggests, around a familiar buck converter. The output signal feeds the inverting input of the operational amplifier (op amp) whose frequency response is affected by a compensation network made around Zf and Rupper. The purpose of this compensation network is to tailor the converter frequency response to make it stable once operated in closed-loop conditions. We will find more complex arrangements later, however. The output of this op amp, Verr(s), flows through the PWM gain block to finally generate the control variable, the duty cycle of the power stage. The power stage is affected by a transfer function H(s). In this configuration, the loop gain is simply T(s) = H(s)G(s)GPWM.
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Figure 3-2: A small-signal representation of the switch-mode converter.
The power converter output, unfortunately, does not solely depend on the control variable d. Some external perturbations contribute to its deviation from the imposed target: they are the input voltage Vin and the output current Iout. We have seen in Chap. 1 how negative feedback reduces these effects. Loop analysis will consist of studying the open-loop gain/phase response of the total chain (the transfer function), most of the time through a Bode plot, and shaping it via the compensation network to stabilize the power supply over the various input/output conditions the converter will encounter in its lifetime.
3.1 Observation Points
Various methods exist to reveal the transfer function of a converter. The simplest one consists of opening the loop—we say breaking the loop—to inject an input signal and observe what is obtained on the other side of the opened path. Capitalizing on the previous figure, we can propose a simple way that the next analysis sketches will adopt (Fig. 3-3).
In this example, a dc source fixes the operating point, and the ac modulation comes in via a coupling capacitor. A network analyzer monitors Vstim and Verr and computes the gain by 20 log10(Verr/Vstim). If this method works great in a SPICE environment, it suffers from a major problem linked to bias point runaway in the presence of high open-loop gains. We therefore do not recommend it for practical experiments.
Observing the voltage on the power stage output will reveal a dc gain and a phase starting from 0°, then becoming negative down to -180° in the case of a second order system (e.g., our voltage-mode CCM buck). If we now look at the voltage delivered by the op amp output, given its inverting configuration, we will add another -180° phase shift to the inverted output stage signal. In classical technical literature, the phase representation of an open-loop system is plotted between 0° and -360°. When it comes to phase margin study, very often, authors purposely omit the -180° inversion brought by the op amp and display the response between 0° and -180°. However, unlike the classical representations, SPICE often bounds its phase display between -180° and +180°. It considers a complete phase rotation when the phase hits 0°.
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Figure 3-3: Operating the loop before the modulating point using an external bias source.
This modulo 2π representation explains why, later on in the text, the phase margin is read as the distance between the open-loop phase trace and the 0° axis. After all, if you observe two waveforms W1 and W2 on an oscilloscope, stating that W2 lags W1 by -270° is similar to say that W2 leads W1 by +90°!
Figure 3-4 shows a typical Bode plot for the CCM buck operated in voltage mode. The upper section depicts the power stage only, H(s). The lower trace represents the total loop gain T(s) after compensation. As indicated in the above paragraph, the observed loop phase starts from 180° in the low frequencies and heads towards 0° if no proper compensation is provided.
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Figure 3-4: A typical Bode plot of a CCM buck power stage, followed by the op amp circuit response (no compensation, no origin pole).
Exploring the ac behavior of Fig. 3-3 can be performed by SPICE via the familiar network LoL and CoL, as already studied before. Figure 3-5 shows it again for reference. Sometimes, a kind of noise appears in ac sweeps using this technique. Adding a series resistor with either CoL or LoL will cure the problem (typically 100 milliohms).
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Figure 3-5: The inductor closes the loop in dc (during bias point calculation) andopens it in ac, blocking all modulation signals coming from the error chain.
The important improvement brought by Fig. 3-5 is the closed-loop dc point you will not have in Fig. 3-3. Any change in the load or the input voltage will automatically adjust the duty cycle to keep the output constant (within the converter capabilities, of course).
As we explained in the previous lines, if you take a power supply and follow Fig. 3-3 opening recommendations, in other words, you physically open the loop and fix a bias point via an external dc source (that you tweak to obtain the right output voltage), then you might encounter difficulties in maintaining the right operating point in the presence of a high dc gain (feedback with an op amp, for instance). A shift of a few millivolts on the external supply due to temperature variations, and the error amplifier hits one of its stops (if it is the upper stop, a loud noise is usually heard!). The transformer method, already tackled in Figs. 2-45 and 2-46, is actually the best and recommended as best practical measurement practice.
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Figure 3-6a and b: Inserting the ac source in series represents another viable solution.
In SPICE, this solution consists of inserting the ac source in series with either the error signal or the output signal. Figure 3-6a and b portrays these possibilities; please note the ac source polarity which appears in series with the preceding signal. The source connections must have satisfied some impedance requirements, however. The - shall connect to a low-impedance point, and the + must go to a high-impedance point. Based on the author's experience, using the LoL/CoL method offers the easiest way with SPICE to probe the transfer function at any point. This is so because the excitation source refers to the ground and does not float. To obtain the loop gain in Fig. 3-5 using IntuScope (IsSpice graphical tool) or Probe (Pspice graphical tool), you simply need to type the following commands:
Gain:
IsSpice: click on dB V(vout)
Probe: type dB(V(vout))
Phase:
IsSpice: click on phase V (vout)
Probe: type Vp (vout)
No further signal manipulations are required. The same applies if you want to probe another node, for instance, the output stage signal, before the op amp divider. On the contrary, if you use the approaches of Fig. 3-6a and b, since the source floats, you need to apply imaginary signal algebra:
Gain:
IsSpice: click on dB V(vout), it gives waveform 1 (W1); click on dB V(vin), it gives waveform 2 (W2). Now plotting W1-W2, you obtain the transfer function.
Probe: type dB(V(vout)/V(vin))
Phase:
IsSpice: click on phase V(vout), it gives waveform 1 (W1), click on phase V(vin), it gives waveform 2 (W2). Now plot W1-W2, you obtain the phase transfer function.
Probe: type Vp(vout) - Vp(vin)
Note: under IntuScope, pressing the keyboard letter b directly plots the Bode diagram on the screen.
As you can see, the floating source requires some manipulations compared to the LoL/CoL method. However, to run a transient analysis, you must absolutely reduce LoL/CoL to 1 pH and 1 pF in order to not disturb the loop. Hence, toggling between ac and transient analysis can quickly become a tedious task. Something you really do not care about with the floating source method as a transient analysis automatically puts this ac source to 0. It thus shields you from toggling between ac and transient schematics. For the sake of simplicity, we will use the LoL/CoL method in this book, but the floating source can be applied the same way.
3.2 Stability CriteriaAmong stability tools (Nyquist, Nichols, . . .), Bode's approach is probably the most popular owing to its simplicity. When other methods require manipulating data in the complex plane, the Bode diagram offers an immediate insight as the transfer function amplitude appears in the frequency domain.
We know that a feedback system takes a portion of the output variable and compares it to a stable reference. It then further "amplifies" the error between these signals, via the loop gain, to generate a corrective action. In other words, if the output voltage deviates from its target—let us assume it increases—the error signal must reduce to instruct the converter to diminish its output. On the contrary, if the output voltage stays below the target, the error voltage will increase to let the converter know that there is a demand for more output voltage. The control action consists of opposing the variation observed on the regulated output, hence the term negative feedback. As the frequency increases, the converter output stage H(s) introduces further delay (we say it "lags") and its gain drops. Combined with the correction loop H(s), a case might quickly appear where the total phase difference between the control signal and the output signal vanishes to 0°. Theory thus shows that if, for any reason, both output and error signals arrive in phase while the gain loop reaches unity (or 0 dB in a log scale), we have built a positive feedback oscillator, delivering a sinusoidal signal at a frequency fixed by the 0 dB crossover point.
When we compensate a power supply, the idea is not to build an oscillator! The design work will thus consist of shaping the correction circuit G(s) to make sure that (1) when the loop gain crosses the 0 dB axis, there exists sufficient phase difference between the error and the output signal and (2) G(s) offers a high gain value in the dc portion to reduce the static error and the output impedance and to improve the input line rejection. This phase difference is called the phase margin (PM). How much phase margin must be selected? Usually, 45° represents the absolute minimum, but rock-solid designs aim for around 70° to 80° phase margin, offering good stability and a fast nonringing transient response.
Figure 3-7 represents the loop gain of a compensated CCM buck voltage-mode converter and highlights the phase margin. We can read a PM greater than 50° and a 0 dB crossover frequency (or a bandwidth) of 4.2 kHz. Please note that PM on this drawing is read as the distance between the phase curve and the 0° line. Sometimes, in textbooks, PM is assessed as the distance between the phase curve and the -180° line. It leads to the same interpretation either way.
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Figure 3-7: The compressed loop gain of a compensated CCM voltage-mode buck converter.
Note that a null phase margin at above or below the 0 dB point offers what is called conditional stability. That is, if the gain moves up or down (the phase shape remaining the same), the unity gain crossover point can coincide with a 0 phase margin, engendering oscillations. What matters is the distance between the 0 dB axis and the point at which danger can occur. This situation can be seen on the right side of Fig. 3-7 where both error and output signals are in phase (0°). If the gain increased by 20 dB, we would be in trouble. . . The gain increase (or decrease in some cases) necessary to reach the 0 dB axis is called the gain margin (GM). Good designs ensure at least a 10 to 15 dB margin to cope with any gain variations, due to loading conditions, component dispersions, ambient temperature, and so on.
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Figure 3-8: In this configuration, the bandwidth did not change, but the phase margin did.
Figure 3-8 represents the same CCM buck but now featuring a reduced phase margin of 25° at the crossover frequency. This is too low. Furthermore, the phase almost hits 0° around 2 kHz. If the gain reduces by 20 dB and crosses 0 dB at that particular point, oscillations will occur, this is the conditional stability described above.
3.3 Phase Margin and Transient Response
A relationship exists between the phase margin of a second-order closed-loop system and the quality coefficient Q of its transfer function [1]. If the phase margin is too small, the peaking induces high output ringing, exactly as in an RLC circuit. On the contrary, if the phase margin becomes too large, it slows down the system: the overshoot goes away but to the detriment of response and recovery speed. An equivalent quality coefficient of 0.5 brings a theoretical phase margin of 76° as highlighted in [1]. It leads to a critically-damped converter, combining response speed and lack of overshoot. Based on this statement, the converter phase margin target must be set to 70°, with a worst case of 45°.
The CCM buck featuring a 4.3 kHz bandwidth was simulated in a transient load step together with various phase margins imposed by the compensation network. Figure 3-9 has collected all transient responses. We can see that a weak phase margin gives birth to oscillations and large overshoots: the system becomes undamped. This is obviously not an acceptable design. As the phase margin increases, the response time slows down a little, but the overshoot fades away. For a 76° phase margin, the overshoot keeps within a 0.5 percent window.
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Figure 3-9: Various step load responses versus phase margin. The undershoot depends on different parameters, including the output capacitor, but the recovery time links to the phase margin.
3.4 Choosing the Crossover Frequency
The crossover frequency is chosen depending on various design factors and constraints. In a power converter, it is possible to approximate its closed-loop output impedance by the output capacitor impedance at the crossover frequency fC. Therefore, the output voltage undershoot level Vp occurring during an output transient step ΔIout can be approximated by the following formula [2](Eq. 3-3)
where Cout is the output capacitor and fc the crossover frequency. Note that this equation holds as long as the output capacitor ESR is less than the reactance of Cout at the crossover frequency, implying that the capacitor is solely held responsible for the undershoot. This condition can be expressed by (Eq. 3-4)
As Fig. 3-9 shows, the undershoot depends on Eq. (3-3), but the recovery time mostly depends on the phase margin at the crossover frequency.
Equation (3-3) can help you make the decision on the crossover value once the output capacitor has been selected based on the needed ripple performance and its rms current capability, for instance. However, there are other limiting factors that you need to consider. For instance, if your converter features a RHP zero, like in CCM boost, buck-boost or flyback converters, then the crossover frequency fc cannot be higher than 30 percent of its worse-case lowest position. It quickly closes the debate! In voltage-mode operated converters, the peaking of the LC network (L or Le) also bounds the crossover frequency: trying to fix fc too close to the resonant frequency f0 of the LC network will bring obvious stability troubles given the phase lag at resonance. Make sure to select f0 at least equal to three times f0 in worse-case conditions.
In absence of RHP zero, however, one-tenth to one-fifth of the switching frequency (10 percent to 20 percent of FSW) looks like a possible target. Extending the crossover frequency can bring additional problems such as noise pick-up: a theoretical design might show adequate PM and GM at the chosen cutoff frequency, but the reduction to practice can show instability because of noise susceptibility brought by the wide loop bandwidth. Do not push the cutoff frequency beyond what you really need to avoid this problem: there is no need for a 15 kHz crossover if a 1 kHz one can do the job transient wise!
3.5 Shaping the Compensation Loop
The stability exercise requires shaping the compensation circuit G(s) in order to provide adequate phase margin at the selected crossover point, together with a high gain in dc. To do so, several compensation circuits can be used, assembling poles and zeros. What we usually need is a phase boost at the crossover frequency to provide the right phase margin. This is done by forcing the loop to cross over with a -1 slope, or -20 dB/decade in the vicinity of the crossover frequency. However, the needed boost is sometimes so large that you cannot reach the crossover frequency you have in mind. You must revise your goal and adopt a more humble target. Let us review the basics about passive filters first, quickly followed by operational amplifier-based circuits.
3.5.1 The Passive Pole
Figure 3-10a represents an RC circuit producing a so-called passive single-pole response. Also known as a low-pass filter, it introduces phase lag (or delay) as the frequency increases. Its Laplace transfer function has the following form (Eq. 3-5):
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The cutoff pulsation of this passive filter, that is, when the dc "gain" reduces by -3 dB, is given by the classical formula (Eq. 3-6)
ωo = 1/RC
Figure 3-10a represents the electrical construction of such a low-pass filter whereas Fig. 3-10b shows its Bode plot.
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Figure 3-10a, b: A single-pole RC network and its frequency response.
A single pole is often inserted in compensation circuits to roll off the gain at a certain point. The rate at which the amplitude goes down is -20 dB by decade. That is, after the cutoff frequency, the amplitude difference at frequencies f1 and f2, where f2 = 10 f1, will be -20 dB. On the Bode plot, this is shown as a "-1" slope, whereas a -40 dB by decade circuit (typically a second-order network) would be designated as a -2 slope. A pole corresponds to a root in the transfer function denominator D(s). Solving for the roots gives an indication of the system stability (please see App. 2B for more details).
3.5.2 The Passive Zero
If the transfer function contains a zero, it appears in the numerator N(s). At the zero frequency, the numerator cancels and nulls the transfer function. Equation (3-7) describes the generalized form of the zero (Eq. 3-7):
Such an expression describes a 0 dB "gain" in dc, followed by a +20 dB/decade slope (a +1 slope) occurring at the zero location. The phase is now positive, as seen in Fig. 3-11a. This is the property of a zero that actually "boosts" the phase, compared to a pole that "lags" the phase. Zeros are thus introduced in G(s) to compensate for excessive phase lag occurring in the power stage response.
Back to the passive circuits, Fig. 3-11b represents a high-pass filter. The transfer function of such a simple RC circuit also contains one pole and one zero, but placed at the origin. It looks like (Eq. 3-8)
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where the cutoff pulsation is the same as Eq. (3-6).
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Figure 3-11a: A single zero network and its frequency response.
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Figure 3-11b, c: A high-pass RC network and its frequency response.
This filter features a low-frequency asymptote of a +20 dB/decade slope (a +1 slope) and high-frequency gain of 1 or 0 dB. Here we have a zero located at the origin nulling the transfer function in dc (s = 0) as Fig. 3-11c portrays.
In all the above equations, a negative numerator root sign signifies a left half-plane zero (LHPZ) position. In some converters, a right half-plane zero (RHPZ) can exist and stability is jeopardized.
3.5.3 Right Half-Plane Zero
The RHPZ is not part of the loop shaping toolbox. You actually undergo a RHPZ rather than create it for stability purposes! Its general form looks pretty much like Eq. (3-7) except that a negative sign appears (Eq. 3-9a):
G(s) = 1 - s/ωo
A RHPZ can be formed by using the circuit in Fig. 3-12a where we can see an active high-pass filter whose inverting output (the negative sign) is summed with the input. The transfer function is easy to derive (Eq. 3-9b):
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with Eq. (3-6) again ruling the cutoff frequency.
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Figure 3-12a: A RHPZ artificially created via an active high-pass filter and an adder.
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Figure 3-12b: The Bode plot looks like a zero, but the phase lags.
As Fig. 3-12b shows, the gain output looks like a traditional zero: a +1 slope of 20 dB/decade with a cutoff frequency imposed by R1 and C1. The difference lies in the phase diagram. Instead of a phase boost, the perfidious RHPZ gives you a phase lag and further degrades the phase margin you strived to save. Right half-plane zeros usually exist in indirect energy transfer converters where energy is first stored (on time) prior to being dumped in the output capacitor (off time). If we take the example of the boost converter, the average diode current equals the load dc current. This diode current Id actually equals the inductor current IL during the off time, or d'Tsw. Its average value can thus be written (Eq. 3-10):
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Suppose we have a 40 percent duty cycle in a CCM-operated boost converter. A sudden load step occurs which, via the feedback loop, pushes the duty cycle to 50 percent. The current in the inductor increases accordingly, but what about the average output current in the diode? It drops because as d' = 1 - d, if d increases, d' shrinks and the output capacitor first discharges instead of increasing! The change goes in the wrong direction until the current builds up in the inductor, bringing the average diode current to its right value and finally lifting up the output voltage. Since it is a closed-loop system, the converter becomes unstable. There is nothing you can do about it, except to severely roll off the bandwidth in order to not undergo the RHPZ additional phase lag.
The RHPZ frequency position unfortunately changes with the duty cycle. The typical rule of thumb recommends that you select a crossover frequency to be around one-third of the lowest RHPZ position. If you try to increase the bandwidth closer to the RHPZ location, you might encounter a problem as the phase lag becomes too large. The RHPZ occurs in CCM operated converters such as buck-boost, boost, or flybacks. The RHPZ disappears in DCM although some academic studies state the presence of one in DCM, but relegated to higher frequencies.
Figure 3-13 plots a converter featuring a RHPZ. In the presence of a load step, the duty cycle suddenly increases. As a result, the inductor current increases as the switch stays closed for a longer time. But as d' has diminished, the diode average current now goes down. This situation translates into a decreasing output voltage, the opposite of what the loop is asking for. Then the average current eventually catches up with the inductor current, and the output voltage rises.
The above lines showed how passive poles and zeros help to shape the loop gain. Unfortunately, used on their own, they do not provide any dc gain, which is badly needed for a low static error, good input rejection, and so on. Associated with operational amplifiers (op amps), these so-called active filters provide the necessary transfer function together with the required amplification. Three different types have been identified.
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Figure 3-13: A RHPZ effect in a boost converter operating in CCM.
3.5.4 Type 1 Amplifier—Active IntegratorImplementing the largest dc gain naturally pushes the usage of an op amp as part of the corrective loop. Rather than cascading the passive networks followed by the high-gain op amp, designers often combined them to form active filters. This is the case for the pure integrator shown in Fig. 3-14a. Note that all configurations are inverting the input signal, but we omitted the minus sign for the sake of clarity.
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Figure 3-14a: A type 1 amplifier. No phase boost, just dc gain.
The transfer function of this pure integral compensator is easy to derive (Eq. 3-11):
It features an origin pole, given by R1 and C1. In dc mode, when the capacitor is open, the op amp open-loop gain fixes the gain. We purposely put it to 60 dB in all the op amp models appearing in the following examples. Then, as the frequency rises, the capacitor impedance drops and reduces the gain with a -1 slope, or -20 dB/decade. The phase curve stays flat and does not provide any boost in phase: cumulating the -180° phase reversal due to the inverting op amp configuration plus the -90° brought by the origin pole, the type 1 compensator permanently rotates the input phase by -270° or +90° when displayed modulo 2π in SPICE. Figure 3-14b shows the resulting frequency sweep brought by such a configuration. Note the action of the op amp origin pole on the dashed curves (30 Hz, 60 dB open-loop gain). It further degrades the phase in higher frequencies and must be accounted for in the final design. Fortunately, SPICE does it naturally as we can pick the op amp model we have selected for the loop design.
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Figure 3-14b: The resulting Bode plot of a type 1 amplifier. Note the action of the op amp origin pole, here active around 30 Hz.
Note that Rlower does not play a role in the ac response as long as the op amp ensures a virtual ground. Why? Simply because the op amp maintains 0 V on the inverting pin, thus making Rlower useless for the ac analysis. However, Rlower helps to select the needed dc output voltage together with R1. See App. 3D for more details.
3.5.5 Type 2 Amplifier—Zero-Pole Pair
The previous amplifier type did not provide us with any phase boost, which we badly need if the phase margin is too low at the desired crossover frequency. Figure 3-15a depicts such a compensator, referenced as a type 2 amplifier. It produces an integrator together with a zero-pole pair.
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Figure 3-15a: A type 2 amplifier can boost the phase.
Its transfer function can be obtained via a few lines of Laplace equations (Eq. 3-12):
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We immediately can see a zero (Eq. 3-13)
a pole at the origin (the integrator) (Eq. 3-14):
and a high-frequency pole (Eq. 3-15)
Figure 3-15b shows how the phase and gain evolve with frequency. We can clearly see the phase increasing between the pole and zero locations. The phase boost depends on the distance between these two points, as we will discover in a few moments. The phase boost peaks right in the geometric mean of ωz and ωp2 which occurs at a pulsation equal to √ωzωp2.
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Figure 3-15b: Type 2 amplifier response. The dashed line illlustrates the op amp origin pole.
3.5.6 Type 2a—Origin Pole Plus a Zero
By suppressing capacitor C2, it is possible to get rid of the high-frequency pole and change the frequency response of the compensation network. Figure 3-16a shows how the type 2 amplifier transforms.
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Figure 3-16a: Suppressing C2 gives a different compensation network and a different Bode plot shape.
The transfer function now becomes (Eq. 3-16)
with a zero described by Eq. (3-17) and a pole at the origin induced by R1 and C1 (Eq. 3-17, 3-18)):
As the frequency increases, the equation reduces to a gain imposed by the two resistors (Eq. 3-19):
Figure 3-16b plots the resulting frequency sweep, again showing the op amp origin pole effect:
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Figure 3-16b: The modified type 2 amplifier featuring a single high-frequency zero. The op amp origin pole effect clearly appears on the graph.
3.5.7 Type 2b—Proportional Plus a Pole
Another variation of the type 2 amplifier consists of adding a resistor to make a proportional amplifier and removing the integral term present with the two previous configurations. Figure 3-17a depicts such an arrangement where a capacitor C1 placed in parallel with the resistor R1 introduces a high-frequency gain, necessary to roll off the gain.
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Figure 3-17a: A type 2b amplifier where proportional control is necessary.
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Figure 3-17b: The dc gain is flat until the high-frequency pole starts to act and imposes a -1 slope decay.
The transient response imposed by this type of amplifier resembles that of Fig. 1-9b, bringing less overshoot in steep load steps. This type of amplifier offers a flat gain imposed by R2 and R1, until the pole imposed by C1 starts to act. The transfer function is (Eq. 3-20):
The pole obeys the classical formula (Eq. 3-21)
Figure 3-17b portrays the ac response brought by such a configuration.
3.5.8 Type 3—Origin Pole Plus Two Coincident Zero-Pole Pairs
The type 3 amplifier is used where a large phase boost is necessary, for instance, in CCM voltage-mode operation of converters which feature a second-order response. Its transfer function can be quickly derived, by calculating the impedance made of Zf = (1/sC2) || {R2 + (1/sC1)} divided by the input series impedance ZI = R1 || {(R3 + (1/sC3)}. See Fig. 3-18a.
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Figure 3-18a: The type 3 amplifier circuitry. Two coincident pole-zero pairs associated with an integrator.
We obtain the following expression, highlighting the pole and zero definitions (Eqs. 3-22, 3-23, 3-24, 3-25a, 3-25b, 3-26):
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Figure 3-18b: The type 3 amplifier introduces an integrator, a double zero, and a double pole.
Figure 3-18b plots the frequency response of the Fig. 3-18a amplifier and shows the slope evolution.
3.5.9 Selecting the Right Amplifier Type
Both the converter type and the transient response you need for your design will guide you through the selection of one particular compensation type.
•Type 1: As it does not offer any phase boost, the type 1 amplifier can be used in converters where the power stage phase shift is small, e.g., in an application where you would like to roll off the gain far away from the resonant frequency of a second-order filter. As in any integral type compensation, it brings the largest overshoot in the presence of a sudden load change. This type is widely used in power factor correction (PFC) applications, for instance, via a transconductance amplifier.
•Type 2: This amplifier is the most widely used and works fine for power stages lagging down to -90° and where the boost brought by the output capacitor ESR must be canceled (to reduce the gain in high frequency). This is the case for current-mode CCM and voltage-mode (direct duty cycle control) converters operated in DCM.
•Type 2a: The application field looks the same as for type 2, but when the output capacitor ESR effect can be neglected, e.g., the zero is relegated to the high-frequency domain, then you can use a type 2a.
•Type 2b: By adding the proportional term, it can help reduce the under- or overshoots in severe design conditions. We have seen that it prevents the output impedance from being too inductive, therefore offering superior transient response. Nevertheless, you pay for it by a reduction of the dc gain, hence a larger static error.
•Type 3: You use this configuration where the phase shift brought by the power stage can reach -180°. This is the case for CCM voltage-mode buck or boost-derived types of converters.
For nearly 100 percent of the applications, a switch-mode converter delivers a parameter—a voltage or a current—whose value must remain constant, independent of various operating conditions, such as the input voltage, the output loading, the ambient temperature. To perform such a task, a portion of the circuit must be insensitive to any of the above variations. This portion is called the reference, usually a voltage source, Vref, which is precise and well stable over temperature. A fraction (α) of the converter output variable (for instance, the output voltage Vout) is permanently compared to this reference. Thanks to a loop that feeds the information back to it, hence the term feedback loop, the controller strives to maintain the theoretical equality between these two levels (Eq. 3-1):
If you go through some power electronics books, you often see the converter modeled using the classical feedback representation. This approach can sometimes confuse the reader as the network divider featuring the α ratio appears in the chain. Unfortunately, if the ratio surely plays a role in setting the dc output, because of the op amp and its virtual ground, its action disappears in the ac analysis. This is discussed in greater detail in App. 3D.
Figure 3-1a portrays the simplified switch-mode converter as it appears on your bench. As we said, thanks to the error amplifier, the whole loop strives to satisfy Eq. (3-1).
Based on Fig. 3-1a, we can draw Fig. 3-1b as a simplified static representation where we purposely reduce the whole chain in a unity-return configuration. From this new drawing, we can write a few equations (Eqs. 3-2):
Here T(0)
represents the static loop gain linking Vout and Vref. The term T(0)/(1 + T(0)) illustrates the static error between the theoretical output value you want and the final measurement you read with a voltmeter once the loop is closed. This is something already seen in Chap. 1. Thus, using a large open-loop gain op amp is key to reducing the static error, but it also helps to provide enough low-frequency gain to fight the rectification ripple in off-line supplies.
Figure 3-2 illustrates the small-signal representation of the power supply. As we explained, the op amp keeps its noninverting pin to zero in small-signal conditions. Therefore, Rlower naturally fades away, and the loop gain is solely fixed by Rupper and Zf. Changing the divider network ratio (α) has no effect on the loop gain, as demonstrated in App. 3D. This is what Fig. 3-2 suggests, around a familiar buck converter. The output signal feeds the inverting input of the operational amplifier (op amp) whose frequency response is affected by a compensation network made around Zf and Rupper. The purpose of this compensation network is to tailor the converter frequency response to make it stable once operated in closed-loop conditions. We will find more complex arrangements later, however. The output of this op amp, Verr(s), flows through the PWM gain block to finally generate the control variable, the duty cycle of the power stage. The power stage is affected by a transfer function H(s). In this configuration, the loop gain is simply T(s) = H(s)G(s)GPWM.
The power converter output, unfortunately, does not solely depend on the control variable d. Some external perturbations contribute to its deviation from the imposed target: they are the input voltage Vin and the output current Iout. We have seen in Chap. 1 how negative feedback reduces these effects. Loop analysis will consist of studying the open-loop gain/phase response of the total chain (the transfer function), most of the time through a Bode plot, and shaping it via the compensation network to stabilize the power supply over the various input/output conditions the converter will encounter in its lifetime.
3.1 Observation Points
Various methods exist to reveal the transfer function of a converter. The simplest one consists of opening the loop—we say breaking the loop—to inject an input signal and observe what is obtained on the other side of the opened path. Capitalizing on the previous figure, we can propose a simple way that the next analysis sketches will adopt (Fig. 3-3).
In this example, a dc source fixes the operating point, and the ac modulation comes in via a coupling capacitor. A network analyzer monitors Vstim and Verr and computes the gain by 20 log10(Verr/Vstim). If this method works great in a SPICE environment, it suffers from a major problem linked to bias point runaway in the presence of high open-loop gains. We therefore do not recommend it for practical experiments.
Observing the voltage on the power stage output will reveal a dc gain and a phase starting from 0°, then becoming negative down to -180° in the case of a second order system (e.g., our voltage-mode CCM buck). If we now look at the voltage delivered by the op amp output, given its inverting configuration, we will add another -180° phase shift to the inverted output stage signal. In classical technical literature, the phase representation of an open-loop system is plotted between 0° and -360°. When it comes to phase margin study, very often, authors purposely omit the -180° inversion brought by the op amp and display the response between 0° and -180°. However, unlike the classical representations, SPICE often bounds its phase display between -180° and +180°. It considers a complete phase rotation when the phase hits 0°.
This modulo 2π representation explains why, later on in the text, the phase margin is read as the distance between the open-loop phase trace and the 0° axis. After all, if you observe two waveforms W1 and W2 on an oscilloscope, stating that W2 lags W1 by -270° is similar to say that W2 leads W1 by +90°!
Figure 3-4 shows a typical Bode plot for the CCM buck operated in voltage mode. The upper section depicts the power stage only, H(s). The lower trace represents the total loop gain T(s) after compensation. As indicated in the above paragraph, the observed loop phase starts from 180° in the low frequencies and heads towards 0° if no proper compensation is provided.
Exploring the ac behavior of Fig. 3-3 can be performed by SPICE via the familiar network LoL and CoL, as already studied before. Figure 3-5 shows it again for reference. Sometimes, a kind of noise appears in ac sweeps using this technique. Adding a series resistor with either CoL or LoL will cure the problem (typically 100 milliohms).
The important improvement brought by Fig. 3-5 is the closed-loop dc point you will not have in Fig. 3-3. Any change in the load or the input voltage will automatically adjust the duty cycle to keep the output constant (within the converter capabilities, of course).
As we explained in the previous lines, if you take a power supply and follow Fig. 3-3 opening recommendations, in other words, you physically open the loop and fix a bias point via an external dc source (that you tweak to obtain the right output voltage), then you might encounter difficulties in maintaining the right operating point in the presence of a high dc gain (feedback with an op amp, for instance). A shift of a few millivolts on the external supply due to temperature variations, and the error amplifier hits one of its stops (if it is the upper stop, a loud noise is usually heard!). The transformer method, already tackled in Figs. 2-45 and 2-46, is actually the best and recommended as best practical measurement practice.
In SPICE, this solution consists of inserting the ac source in series with either the error signal or the output signal. Figure 3-6a and b portrays these possibilities; please note the ac source polarity which appears in series with the preceding signal. The source connections must have satisfied some impedance requirements, however. The - shall connect to a low-impedance point, and the + must go to a high-impedance point. Based on the author's experience, using the LoL/CoL method offers the easiest way with SPICE to probe the transfer function at any point. This is so because the excitation source refers to the ground and does not float. To obtain the loop gain in Fig. 3-5 using IntuScope (IsSpice graphical tool) or Probe (Pspice graphical tool), you simply need to type the following commands:
Gain:
IsSpice: click on dB V(vout)
Probe: type dB(V(vout))
Phase:
IsSpice: click on phase V (vout)
Probe: type Vp (vout)
No further signal manipulations are required. The same applies if you want to probe another node, for instance, the output stage signal, before the op amp divider. On the contrary, if you use the approaches of Fig. 3-6a and b, since the source floats, you need to apply imaginary signal algebra:
Gain:
IsSpice: click on dB V(vout), it gives waveform 1 (W1); click on dB V(vin), it gives waveform 2 (W2). Now plotting W1-W2, you obtain the transfer function.
Probe: type dB(V(vout)/V(vin))
Phase:
IsSpice: click on phase V(vout), it gives waveform 1 (W1), click on phase V(vin), it gives waveform 2 (W2). Now plot W1-W2, you obtain the phase transfer function.
Probe: type Vp(vout) - Vp(vin)
Note: under IntuScope, pressing the keyboard letter b directly plots the Bode diagram on the screen.
As you can see, the floating source requires some manipulations compared to the LoL/CoL method. However, to run a transient analysis, you must absolutely reduce LoL/CoL to 1 pH and 1 pF in order to not disturb the loop. Hence, toggling between ac and transient analysis can quickly become a tedious task. Something you really do not care about with the floating source method as a transient analysis automatically puts this ac source to 0. It thus shields you from toggling between ac and transient schematics. For the sake of simplicity, we will use the LoL/CoL method in this book, but the floating source can be applied the same way.
3.2 Stability CriteriaAmong stability tools (Nyquist, Nichols, . . .), Bode's approach is probably the most popular owing to its simplicity. When other methods require manipulating data in the complex plane, the Bode diagram offers an immediate insight as the transfer function amplitude appears in the frequency domain.
We know that a feedback system takes a portion of the output variable and compares it to a stable reference. It then further "amplifies" the error between these signals, via the loop gain, to generate a corrective action. In other words, if the output voltage deviates from its target—let us assume it increases—the error signal must reduce to instruct the converter to diminish its output. On the contrary, if the output voltage stays below the target, the error voltage will increase to let the converter know that there is a demand for more output voltage. The control action consists of opposing the variation observed on the regulated output, hence the term negative feedback. As the frequency increases, the converter output stage H(s) introduces further delay (we say it "lags") and its gain drops. Combined with the correction loop H(s), a case might quickly appear where the total phase difference between the control signal and the output signal vanishes to 0°. Theory thus shows that if, for any reason, both output and error signals arrive in phase while the gain loop reaches unity (or 0 dB in a log scale), we have built a positive feedback oscillator, delivering a sinusoidal signal at a frequency fixed by the 0 dB crossover point.
When we compensate a power supply, the idea is not to build an oscillator! The design work will thus consist of shaping the correction circuit G(s) to make sure that (1) when the loop gain crosses the 0 dB axis, there exists sufficient phase difference between the error and the output signal and (2) G(s) offers a high gain value in the dc portion to reduce the static error and the output impedance and to improve the input line rejection. This phase difference is called the phase margin (PM). How much phase margin must be selected? Usually, 45° represents the absolute minimum, but rock-solid designs aim for around 70° to 80° phase margin, offering good stability and a fast nonringing transient response.
Figure 3-7 represents the loop gain of a compensated CCM buck voltage-mode converter and highlights the phase margin. We can read a PM greater than 50° and a 0 dB crossover frequency (or a bandwidth) of 4.2 kHz. Please note that PM on this drawing is read as the distance between the phase curve and the 0° line. Sometimes, in textbooks, PM is assessed as the distance between the phase curve and the -180° line. It leads to the same interpretation either way.
Note that a null phase margin at above or below the 0 dB point offers what is called conditional stability. That is, if the gain moves up or down (the phase shape remaining the same), the unity gain crossover point can coincide with a 0 phase margin, engendering oscillations. What matters is the distance between the 0 dB axis and the point at which danger can occur. This situation can be seen on the right side of Fig. 3-7 where both error and output signals are in phase (0°). If the gain increased by 20 dB, we would be in trouble. . . The gain increase (or decrease in some cases) necessary to reach the 0 dB axis is called the gain margin (GM). Good designs ensure at least a 10 to 15 dB margin to cope with any gain variations, due to loading conditions, component dispersions, ambient temperature, and so on.
Figure 3-8 represents the same CCM buck but now featuring a reduced phase margin of 25° at the crossover frequency. This is too low. Furthermore, the phase almost hits 0° around 2 kHz. If the gain reduces by 20 dB and crosses 0 dB at that particular point, oscillations will occur, this is the conditional stability described above.
3.3 Phase Margin and Transient Response
A relationship exists between the phase margin of a second-order closed-loop system and the quality coefficient Q of its transfer function [1]. If the phase margin is too small, the peaking induces high output ringing, exactly as in an RLC circuit. On the contrary, if the phase margin becomes too large, it slows down the system: the overshoot goes away but to the detriment of response and recovery speed. An equivalent quality coefficient of 0.5 brings a theoretical phase margin of 76° as highlighted in [1]. It leads to a critically-damped converter, combining response speed and lack of overshoot. Based on this statement, the converter phase margin target must be set to 70°, with a worst case of 45°.
The CCM buck featuring a 4.3 kHz bandwidth was simulated in a transient load step together with various phase margins imposed by the compensation network. Figure 3-9 has collected all transient responses. We can see that a weak phase margin gives birth to oscillations and large overshoots: the system becomes undamped. This is obviously not an acceptable design. As the phase margin increases, the response time slows down a little, but the overshoot fades away. For a 76° phase margin, the overshoot keeps within a 0.5 percent window.
The crossover frequency is chosen depending on various design factors and constraints. In a power converter, it is possible to approximate its closed-loop output impedance by the output capacitor impedance at the crossover frequency fC. Therefore, the output voltage undershoot level Vp occurring during an output transient step ΔIout can be approximated by the following formula [2](Eq. 3-3)
Equation (3-3) can help you make the decision on the crossover value once the output capacitor has been selected based on the needed ripple performance and its rms current capability, for instance. However, there are other limiting factors that you need to consider. For instance, if your converter features a RHP zero, like in CCM boost, buck-boost or flyback converters, then the crossover frequency fc cannot be higher than 30 percent of its worse-case lowest position. It quickly closes the debate! In voltage-mode operated converters, the peaking of the LC network (L or Le) also bounds the crossover frequency: trying to fix fc too close to the resonant frequency f0 of the LC network will bring obvious stability troubles given the phase lag at resonance. Make sure to select f0 at least equal to three times f0 in worse-case conditions.
In absence of RHP zero, however, one-tenth to one-fifth of the switching frequency (10 percent to 20 percent of FSW) looks like a possible target. Extending the crossover frequency can bring additional problems such as noise pick-up: a theoretical design might show adequate PM and GM at the chosen cutoff frequency, but the reduction to practice can show instability because of noise susceptibility brought by the wide loop bandwidth. Do not push the cutoff frequency beyond what you really need to avoid this problem: there is no need for a 15 kHz crossover if a 1 kHz one can do the job transient wise!
3.5 Shaping the Compensation Loop
The stability exercise requires shaping the compensation circuit G(s) in order to provide adequate phase margin at the selected crossover point, together with a high gain in dc. To do so, several compensation circuits can be used, assembling poles and zeros. What we usually need is a phase boost at the crossover frequency to provide the right phase margin. This is done by forcing the loop to cross over with a -1 slope, or -20 dB/decade in the vicinity of the crossover frequency. However, the needed boost is sometimes so large that you cannot reach the crossover frequency you have in mind. You must revise your goal and adopt a more humble target. Let us review the basics about passive filters first, quickly followed by operational amplifier-based circuits.
3.5.1 The Passive Pole
Figure 3-10a represents an RC circuit producing a so-called passive single-pole response. Also known as a low-pass filter, it introduces phase lag (or delay) as the frequency increases. Its Laplace transfer function has the following form (Eq. 3-5):
Figure 3-10a represents the electrical construction of such a low-pass filter whereas Fig. 3-10b shows its Bode plot.
A single pole is often inserted in compensation circuits to roll off the gain at a certain point. The rate at which the amplitude goes down is -20 dB by decade. That is, after the cutoff frequency, the amplitude difference at frequencies f1 and f2, where f2 = 10 f1, will be -20 dB. On the Bode plot, this is shown as a "-1" slope, whereas a -40 dB by decade circuit (typically a second-order network) would be designated as a -2 slope. A pole corresponds to a root in the transfer function denominator D(s). Solving for the roots gives an indication of the system stability (please see App. 2B for more details).
3.5.2 The Passive Zero
If the transfer function contains a zero, it appears in the numerator N(s). At the zero frequency, the numerator cancels and nulls the transfer function. Equation (3-7) describes the generalized form of the zero (Eq. 3-7):
Back to the passive circuits, Fig. 3-11b represents a high-pass filter. The transfer function of such a simple RC circuit also contains one pole and one zero, but placed at the origin. It looks like (Eq. 3-8)
This filter features a low-frequency asymptote of a +20 dB/decade slope (a +1 slope) and high-frequency gain of 1 or 0 dB. Here we have a zero located at the origin nulling the transfer function in dc (s = 0) as Fig. 3-11c portrays.
In all the above equations, a negative numerator root sign signifies a left half-plane zero (LHPZ) position. In some converters, a right half-plane zero (RHPZ) can exist and stability is jeopardized.
3.5.3 Right Half-Plane Zero
The RHPZ is not part of the loop shaping toolbox. You actually undergo a RHPZ rather than create it for stability purposes! Its general form looks pretty much like Eq. (3-7) except that a negative sign appears (Eq. 3-9a):
A RHPZ can be formed by using the circuit in Fig. 3-12a where we can see an active high-pass filter whose inverting output (the negative sign) is summed with the input. The transfer function is easy to derive (Eq. 3-9b):
Suppose we have a 40 percent duty cycle in a CCM-operated boost converter. A sudden load step occurs which, via the feedback loop, pushes the duty cycle to 50 percent. The current in the inductor increases accordingly, but what about the average output current in the diode? It drops because as d' = 1 - d, if d increases, d' shrinks and the output capacitor first discharges instead of increasing! The change goes in the wrong direction until the current builds up in the inductor, bringing the average diode current to its right value and finally lifting up the output voltage. Since it is a closed-loop system, the converter becomes unstable. There is nothing you can do about it, except to severely roll off the bandwidth in order to not undergo the RHPZ additional phase lag.
The RHPZ frequency position unfortunately changes with the duty cycle. The typical rule of thumb recommends that you select a crossover frequency to be around one-third of the lowest RHPZ position. If you try to increase the bandwidth closer to the RHPZ location, you might encounter a problem as the phase lag becomes too large. The RHPZ occurs in CCM operated converters such as buck-boost, boost, or flybacks. The RHPZ disappears in DCM although some academic studies state the presence of one in DCM, but relegated to higher frequencies.
Figure 3-13 plots a converter featuring a RHPZ. In the presence of a load step, the duty cycle suddenly increases. As a result, the inductor current increases as the switch stays closed for a longer time. But as d' has diminished, the diode average current now goes down. This situation translates into a decreasing output voltage, the opposite of what the loop is asking for. Then the average current eventually catches up with the inductor current, and the output voltage rises.
The above lines showed how passive poles and zeros help to shape the loop gain. Unfortunately, used on their own, they do not provide any dc gain, which is badly needed for a low static error, good input rejection, and so on. Associated with operational amplifiers (op amps), these so-called active filters provide the necessary transfer function together with the required amplification. Three different types have been identified.
3.5.4 Type 1 Amplifier—Active IntegratorImplementing the largest dc gain naturally pushes the usage of an op amp as part of the corrective loop. Rather than cascading the passive networks followed by the high-gain op amp, designers often combined them to form active filters. This is the case for the pure integrator shown in Fig. 3-14a. Note that all configurations are inverting the input signal, but we omitted the minus sign for the sake of clarity.
The transfer function of this pure integral compensator is easy to derive (Eq. 3-11):
Note that Rlower does not play a role in the ac response as long as the op amp ensures a virtual ground. Why? Simply because the op amp maintains 0 V on the inverting pin, thus making Rlower useless for the ac analysis. However, Rlower helps to select the needed dc output voltage together with R1. See App. 3D for more details.
3.5.5 Type 2 Amplifier—Zero-Pole Pair
The previous amplifier type did not provide us with any phase boost, which we badly need if the phase margin is too low at the desired crossover frequency. Figure 3-15a depicts such a compensator, referenced as a type 2 amplifier. It produces an integrator together with a zero-pole pair.
Its transfer function can be obtained via a few lines of Laplace equations (Eq. 3-12):
3.5.6 Type 2a—Origin Pole Plus a Zero
By suppressing capacitor C2, it is possible to get rid of the high-frequency pole and change the frequency response of the compensation network. Figure 3-16a shows how the type 2 amplifier transforms.
As the frequency increases, the equation reduces to a gain imposed by the two resistors (Eq. 3-19):
3.5.7 Type 2b—Proportional Plus a Pole
Another variation of the type 2 amplifier consists of adding a resistor to make a proportional amplifier and removing the integral term present with the two previous configurations. Figure 3-17a depicts such an arrangement where a capacitor C1 placed in parallel with the resistor R1 introduces a high-frequency gain, necessary to roll off the gain.
The transient response imposed by this type of amplifier resembles that of Fig. 1-9b, bringing less overshoot in steep load steps. This type of amplifier offers a flat gain imposed by R2 and R1, until the pole imposed by C1 starts to act. The transfer function is (Eq. 3-20):
3.5.8 Type 3—Origin Pole Plus Two Coincident Zero-Pole Pairs
The type 3 amplifier is used where a large phase boost is necessary, for instance, in CCM voltage-mode operation of converters which feature a second-order response. Its transfer function can be quickly derived, by calculating the impedance made of Zf = (1/sC2) || {R2 + (1/sC1)} divided by the input series impedance ZI = R1 || {(R3 + (1/sC3)}. See Fig. 3-18a.
We obtain the following expression, highlighting the pole and zero definitions (Eqs. 3-22, 3-23, 3-24, 3-25a, 3-25b, 3-26):
Figure 3-18b plots the frequency response of the Fig. 3-18a amplifier and shows the slope evolution.
3.5.9 Selecting the Right Amplifier Type
Both the converter type and the transient response you need for your design will guide you through the selection of one particular compensation type.
•Type 1: As it does not offer any phase boost, the type 1 amplifier can be used in converters where the power stage phase shift is small, e.g., in an application where you would like to roll off the gain far away from the resonant frequency of a second-order filter. As in any integral type compensation, it brings the largest overshoot in the presence of a sudden load change. This type is widely used in power factor correction (PFC) applications, for instance, via a transconductance amplifier.
•Type 2: This amplifier is the most widely used and works fine for power stages lagging down to -90° and where the boost brought by the output capacitor ESR must be canceled (to reduce the gain in high frequency). This is the case for current-mode CCM and voltage-mode (direct duty cycle control) converters operated in DCM.
•Type 2a: The application field looks the same as for type 2, but when the output capacitor ESR effect can be neglected, e.g., the zero is relegated to the high-frequency domain, then you can use a type 2a.
•Type 2b: By adding the proportional term, it can help reduce the under- or overshoots in severe design conditions. We have seen that it prevents the output impedance from being too inductive, therefore offering superior transient response. Nevertheless, you pay for it by a reduction of the dc gain, hence a larger static error.
•Type 3: You use this configuration where the phase shift brought by the power stage can reach -180°. This is the case for CCM voltage-mode buck or boost-derived types of converters.
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